Static Scheduling of Instructions on Micronet-based Asynchronous Processors - Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International S
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چکیده
This paper investigates issues which impinge on the design of static instruction schedulers for micronetbased asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimtsed with MAP-specific heuristics. Their performance on some program graphs are presented and conclusions are drawn on the suitability of M A P as targets for ILP compilers.
منابع مشابه
Static scheduling of instructions on micronet-based asynchronous processors
This paper investigates issues which impinge on the design of static instruction schedulers for micronet-based asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-speciic heuristics. Their performance on some program graphs are presented and con...
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